Radix reconversion apparatus



April 15,1969

F. c. BECKER 3,439,154

' RADIX RECONVERSION APPARATUS Filed Feb. 9. 1966 Sheet i o4 START Fig.2.

-T RESET RESET C SOl-SQZ W I. X T. Y em RESTART cuc o CDC=0 DACC=0 CLOCK CT RA 6 CT GPC CARRY T SET 0 CT CUC AAR=| CT'D ACC AAR=I ,1 SET'W CUC=24 GPC=0 T CLOCK CUC- CDC SETY =5+O.

. i I SET X W CUC=0 RESET W SET SOI United States Patent O 3,439,154 RADIX RECONVERSION APPARATUS Frederick C. Becker, Dearborn Heights, Mich., assignor to Burroughs Corporation, Detroit, Mich., a corporation of Michigan Filed Feb. 9, 1966, Ser. No. 526,155 Int. Cl. G06f /02 US. Cl. 235-155 Claims This invention relates to radix reconversion apparatus for computers, and more particularly to electronic apparatus for reconverting to sterling currency a temporarily stored pence equivalent resultant.

In business transactions involving sterling currency,

' which contains base ten, twelve, and twenty values, automatic computers frequently manipulate mathematically the sterling factors for ease of calculation. Because of the mathematical manipulation, the computer derives a resultant which, though arithmetically correct, is not in sterling radix form. For that reason, the resultant must be reconverted to proper form. Heretofore, reconversion apparatus have been complex, costly, separated from the computer elements, and required numerous time consuming operational steps.

Accordingly, the primary object of this invention is to provide an improved reconversion apparatus which is operable upon a multidigit pence resultant and produces the equivalent of the resultant in pounds, shillings, and pence.

Another object of this invention is to provide a simplified electronic reconversion apparatus which is compatible with and shares portions of an electronic computer.

Another object of this invention is to provide radix reconversion apparatus which can temporarily extend some of its internal computational radices.

A further object of this invention is to provide radix reconversion apparatus which is controlled for a repetition of simple operational sequences.

Other objects and features of this invention will become apparent by reference to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a logic diagram of the elements of the invention coupled so as to remove the pence resultant from the resultant accumulator and store it in buffer memories;

FIG. 2 is a flow chart of the operational sequence performed by the logic elements shown in FIG. 1;

FIG. 3 is a logic diagram of the elements of the invention required to reconvert the contents in the buffer memories to a sterling quantity and transmit that quantity to the primary accumulator;

FIG. 4 is a flow chart of the operational sequence performed by the logic elements shown in FIG. 3;

FIG. 5 is a logic diagram of the elements of the invention required to terminate reconversion or to select the next portion of the resultant for reconversion and recommence the reconversion operations;

FIG. 6 is a flow chart of the operational sequence performed by the logic elements shown in FIG. 5; and

FIG. 7 is a presentation of a sample problem.

In the following disclosure of my invention, the description of several of the logic elements will be enhanced by reference to US. patent application S.N. 448,711 to Radcliffe et al., now Patent No. 3,361,898, and assigned to the assignee of the present invention. The Radcliffe application relates to a multiplying system which stores its 3,439,154 Patented Apr. 15, 1969 ICC product as a plurality of decimal digits. For purposes of the present invention, it will be assumed that the decimal product, or resultant as it will be termed hereinafter, arises from calculations involving a sterling factor and, therefore, requires reconversion to sterling. Inasmuch as the present invention is contemplated for use with a computer that provides the decimal resultant, that computer will be assumed to be in the system disclosed in the Radcliffe application.

With reference to the logic diagram of FIG. 1, there is shown a resultant accumulator RA11 which, at the beginning of the radix reconversion, stores a plurality of decimal digits representing the pence equivalent of a resultant sterling computation. The RA11 comprises a plurality of discretely addressable base ten stages serially coupled for propagation of tens carries to the next higher stage. Carries are added to the next higher stage upon the application of a CARRY ENABLE signal CE, as shown in FIG. 3. The resultant accumulator could be similar to the product accumulator PA207 shown in FIG. 13 of the Radcliffe application.

The addressing of the stages of the RA is controlled by an accumulator address register AAR13 which may take the form of a binary to decimal encoding and decoding circuit similar to the AAR235 shown in FIGS. 15-17 of the Radcliffe application. Although the Radcliife application places considerable emphasis on the circular nature of the PA and its preshift capabilities which are directed through the AAR, the subject reconversion apparatus does not have need for these special features, for reconversion is accomplished by a single sequential addressing of each stage of the RA from the most significant to the least significant decimal position.

Let it be assumed that the RA comprises twelve stages numbered from one to twelve in increasing decimal positional value. Similarly, let it be assumed that the AAR has twelve positions, one through eleven and zero, for discretely addressing the accumulator stages one through twelve respectively.

Each AAR position has a true and a false signal condition. When a particular position is true, it enables a correspondingly numbered COUNT input line CT in the RA11 to thereby enable the associated stage in the resultant accumulator. The CT line also serves as the input for pulses to be stored .by the RA.

The source of pulses is a CLOCK 15, which may be a free running multivibrator similar to that shown in FIG. 6 of the Radcliffe application and logically implemented in FIG. 11 thereof as the CLOCK 167. As shown in FIG. 1, the clock pulses, CLK, are steered through the AAR13 and are applied to the preselected stage in the RA11 via the CT line.

The CLK pulses are also coupled to a group pulse counter GPC17 which may be a conventional binary to decimal counter such as the GPC16-9 shown in FIG. 12 of the radcliffe application. Although reconversion to sterling must recognize that there are twelve pence in a shilling and twenty shillings or two hundred and forty pence in a pound, the GPC17 need not be a multiradix counter. A base ten, forward advancing and recirculating counter is all the present apparatus requires. Each time the GPC is advanced from one through nine and then back to zero, a GPC=0 signal is generated and is employable for turning off the CLOCK 15', as shown in FIG. 1.

The CLOCK is turned on by positive switching levels 3 generated from a pair of bistable devices 19 and 21 respectively labeled SQI and SQ2. The setting and resetting of these devices initiate three operational sequences which constitute the entire reconversion operation. These sequences are initiated by the following signals:

Q 1 -'@=Sequence One SQ1-2=Sequence Two SQ1-SQ2=Sequence Three The following trio of counters comprise the remaining major elements of this invention:

Base twenty-four count up counter CUC23 Base twenty-four count down counter CDCZS Base twelve pence accumulator D ACC27.

The CUC23 advances from zero to twenty-three and cyclically back to zero. The CDCZS steps incrementally downward from twenty-three to zero and then is recycled to the count of twenty-three upon receipt of the next input. The D ACC advances from zero to eleven and cyclically back to zero. These counters could be designed in several different ways by those skilled in the art. One such design might employ a plurality of serially coupled complementing bistable devices such as that shown in FIG. 8 of the Radcliffe application. Four such devices would be sufficient for the base twelve counter and five devices for the base twenty-four counters.

A further design criterion for the CUC and CDC is that the contents of the OUC are to be transferable en masse, in a parallel sense, to the then empty CDC. Simple gating between the outputs of each bistable device in the CUC and the inputs of the positionally similar devices in the CDC can provide an on demand transfer of data. It will become apparent that the C-UC and the CDC act as buffer memories.

In addition to the above described logic elements, the subject invention comprises the following four bistable devices which are shown in FIG. 1 with the accompanying reference numerals: C-29, W-31, X-33, and Y-35. These bistable devices as well as the devices SQl and SQ2 may be of the set-reset type, shown in FIG. 7 of the Radcliffe application.

The three operational sequences are performed discretely upon each decimal or pence value stored in the RA11. During the first sequence, the decimal value in the addressed stage of the RA is cleared out and is entered into the CUC23. If there were any remainder from operations upon the just previously addressed stage, it is added in the OUC to the newly entered value. The total stored in the C-UC is then transferred to the CDC 25 and the CUC is cleared. When the least significant accumulator stage is addressed, its contents are entered into the D ACC27 rather than the CUC23.

During the second sequence, reconversion is performed. When stages twelve through three are addressed, the object is to extract the whole number of pounds from the pence values. This object is attained by multiplying each pence value by ten, dividing by two and four tenths, and employing an inherent decimal shift of two places to obtain an effective division by two hundred and forty.

This division is accomplished by advancing the CUC ten times as fast as the CDC is being counted down to zero and transferring each twenty-fourth count pulse from the OUC to the initially addressed stage of the RA. Any remaining amount is retained in the CUC to be added to the value entered during the next occurrence of the first sequence.

During the second sequence, and when stage number two of the RA is being addressed, its contents, increased by the remainder from the operation upon the contents of the third stage, could total more than two-hundred and forty pence, i.e., more than one pound. To facilitiate the reconversion of this pound value to the units of pounds position in the RA, its third stage position, the OUC and the CDC are counted at a one to one relationship, not

4 at the normal ten to one ratio. Any carry out from the CUC is entered directly into the third stage of the RA and the remainder retained in the CUC for addition with the pence value stored in the least significant, first stage of the RA.

During the second sequence, and when the first stage of the RA is being addressed, the CDC and the base twelve D AAC27 cooperate similarly to the previous coaction of the CUC and the CDC. However, in this instance the sum of ten times the remainder held in the CUC and the pence value in the first stage are transferred into the D ACC and divided by twelve to extract the number of shillings, which are counted into the first stage with a carry, when appropriate, into the second stage. The remainder in the D ACC is the true pence figure.

In the third operational sequence, the AAR13 is counted down one position and the three sequences again initiated for the next less significant RA stage. When the AAR is cycled back to its zero position, the third sequence generates a stop reconversion signal.

The subject apparatus next will be described in detail with particular emphasis upon the three operational sequences and the reconversion of 19,941 pence to 83-1-9 as shown in the sample problem in FIG. 7. With reference to the top two lines of FIG. 7, the pence digits 19,941 are assumed to be stored in the RA positions or stages five through one respectively and, though not shown, zeros are contained in stages twelve through six.

Reconversion is initiate-d by a START signal which may come from the computer sometime subsequent to its storage of the pence values in the RA11. As shown on the fiow chart of FIG. 2, the START signal resets the bistable devices SQl, SQ2, C, W, X, and Y and also sets to zero the multicount elements AAR, GPC, CLIC, CDC and D ACC. FIG. 1 illustrates the coupling of the START signal to the above named devices and elements by means of unlabeled jack-type inputs. FIGS. 3 and 5 employ the same input notation to represent logic'conditions created during the previous operational sequence.

Setting the AAR to zero addresses the most significant position of the RA, which is its twelfth stage; however, in the present example stages twelve through six contain zeros and, therefore, produce no reconverted values. Nevertheless, the three sequences, or to be more exact, sequences one and three and the latter portion of sequence two are initiated for each positional value twelve through six of the RA. Since operations upon zeros are not as illustrative of the reconversion apparatus and may be atypical, the following description will commence with the AAR having a value of five, thereby addressing the fifth stage of the RA which stores the digit 1.

Except for the advanced status of the AAR13, allother logic elements are in their initial start condition. The high signals from the "0 side of the reset SQl and SQ2 devices are gated together and applied to the ON input of the CLOCK 15 to start a train of CLK pulses which are directed by the AAR to the fifth stage of the RA via its CT input; The 6 signal from the bistable device 29 is employed to enable the CT input. The CLK pulses also are applied directly into the base ten GPC17. Since the fifth stage initially contains the value of 1, the application of nine more CLK pulses fills that stage, i.e., sets it to the cleared value of zero, and produces a carry pulse. As shown in FIG. 1, the zero, or carry out signal is applied to the input of the bistable device 29, which is labeled C for carry, to set it. The setting of the device C causes its "0 output to go low and inhibit the CT input to the RA. Inasmuch as the carry enable line CE is not energized by the START signal and therefor not shown in FIG. 1, the carry out from the fifth stage is not coupled to the sixth stage.

As best illustrated in FIG. 2, the setting of the device C and the position of the AAR control the flow of CLK pulses from the CLOCK into the CT inputs of the OUC23 and the D ACC27. As the AAR is now set to five, the

AAR-:I signal is high and the AAR=1 is low; thus, the CUC is enabled to receive the CLK pulses and the D ACC is inhibited. Accordingly, the next CLK pulse, which is the tenth to be generated, is applied to the CUC to step it from to 1.

If the CUC were storing a remainder from the previous sequence of operations and the sum of that remainder and the contents of the presently addressed stage of the RA exceeded or equaled twenty-four, the radix of the CUC, then the bistable device W would be set as the CUC is stepped from twenty-three to zero. 'In this manner the W device 31 extends the counting capacity of the CUC to a maximum of thrity-two, the sum of the maximum contents of an RA stage and a maximum remainder. The need for such extended capacity will become apparent during the subsequent description.

Since all ten CLK pulses also are being applied to the base ten GPC, it is recycled to zero and produces a GPC=0 signal which, as shown in FIGS. 1 and 2, is applied to the CLOCK to turn it off. Thus, as shown on line three of the RA POSS column of FIG. 7, the CUC temporarily stores the value of 1 which was previously stored in the fifth stage of the RA which is now clear.

The GPO=0 signal also is applied to the CUC to cause the direct transfer en masse of the contents of the CUC to the CDC via a cable labeled T. As shown in line four of FIG. 7, the digit 1 is thereby placed into the CDC. The cable T is also gated with the 1 output of the device W and is coupled to the set inbut of the bistable device X to set it upon the CUC to CDC transfer, if the device W was set during the application of the CLK pulses to the CUC. The device X is functionally similar to the device W in that it extends the capacity of the CDC as will be demonstrated hereinafter. In the present example, the addressing of the fifth stage of the RA does not cause the W device 31 to be set; therefore, the X device 33 also is not set.

The GPC=0 signal is also employable in setting the bistable device Y, by being gated with the CUC=6 output as well as the combined gating of the CUC=O output and the W signal. By that logic, the Y device 35 is set as a consequence of the C-UC storing a value other than zero at any time during the first operational sequence prior to its transfer of data to the CDC. As demonstrated hereinbelow, the status of the device Y determines a portion of the second operational sequence. Since the CUC contained in the value 1, the CUC=6 output became active and enabled the setting of the device Y. Additionally, the GPC=O signal is employed at the end of the first operational sequence to reset the OUC to zero, reset the r device W, if it had been set earlier, and set the SQ1 device.

The 1 output from the now set SQ1 device and the 0 output from the initially reset SQ2 device are gated together to trigger the second operational sequence which is depicted logically in FIG. 3 and by the flow chart in FIG. 4. The SQ1-W signal is coupled to the CE input of the RA11 to thereafter enable the propagation of tens carries from one stage or column in the RA to the next more significant column.

The SQ1-W Signal is also coupled to the CLOCK 15 to start the generation of a train of CLK pulses which are applied to the CT input of the GPC17 and to the CT input of either the CUC23- or the D ACC27 depending upon the gating conditions shown on the flow chart in FIG. 4. Since the AAR is presently addressing the fifth column in the RA, the AAR= output signal is logically true and all other AAR output levels are false. Also, in the first operation sequence the Y device 35 was set and is now generating the Y signal. Hence an AAR= 1 +-Y gating condition is met and CLK pulses are applied to the CUC and not the D ACC.

After ten CLK pulses are generated, the base ten GPC again is returned to its zero count position and emits the second GPC=0 signal which now is coupled to the CDC25 to count it down one step from its previous position of one to zero. Thus, the ten pulses are entered into the base twenty-four CUC while only one pulse is introduced into the CDC. If, as a result of the first operational sequence, the CDC contained a value greater than one, then several groups of ten CLK pulses would be applied to the CUC as the CDC is stepped down to zero. Also, if during the counting down of the CDC the CUC receives more than its radix capacity, it would produce a carry signal which would be counted into an appropriate RA stage, as will be described during the sequential operations upon contents of the fourth RA stage in the example problem.

From the already presented portion of the second operational sequence it now should be appreciated that for each count down of the CDC, the CUC has been counted up by ten and then hasbeen divided by twenty-four as representing a carry into the addressed column of the RA. This would appear to create a relationship between the value initially stored in the CUC and the carries therefrom of one to two and four tenths; however, by inserting the carry from the CUC into the same RA column as initially addressed and since the number of pence in a pound is two decimal positions lower than that of a pound (240d=100s00d), there is produced the required two-hundred and forty to one relationship. In the present example, the initial CUC value of one is transposed into a quotient of zero and a remainder of ten in the CUC, as depicted on line six of FIG. 7 under the fifth RA position column.

The stepping down of the CDC to zero produces a CDC=0 signal which is gated with the X signal from the 0 output of the previously reset device 33 and is coupled to the device Y to reset it and generate a Y signal. The CD0 0 signal is also gated with the GPC=0 signal and is applied to the reset input of the device X to reset it and elicit the X signal if it were not already present. In this manner, had the W and X devices been set in the first operational sequence, then the CDC=O-X condition would not be present the first time the CDC is stepped down to zero, but would exist upon the second occurrence of the CDC=0 signal. As a consequence, the CDC radix is extended beyond twenty-four whenever the the CUC radix is extended beyond twenty-four in the preceding operational sequence.

The Y signal is coupled to the CLOCK to turn it off; it is also gated with the AAR=T signal to advance the count position of the AAR, in this instance from five to six; and finally it is applied to the set input of the SQ2 device to set it and terminate the second operational sequence.

Had the AAR been addressing the first or second RA stages, the AAR=1 or AAR=2 signals would have modified the second operational sequence, as will be demonstrated hereinafter. If in the first operational sequence the device Y had not been set, then the second sequence would have been skipped up to the last step when the Y signal is inserted as shown in FIG. 4. During the processing of RA stages twelve through six, each containing zeros in this example problem, the Y device would not have been set in the first operational sequence.

The setting of the SQZ device 21 at the end of the second operational sequence generates a true signal from its 1 output which is gated with the 1 output from the SQ1 device 19 which was set at the end of the first operational sequence and thereby forms the SQI-SQZ condition which initiates the third operational sequence and is coupled to the CLOCK 15 to turn it on. As shown in FIGS. 5 and 6, the ensuing train of CLK pulses is applied to both the AAR13 and the GPC17 to advance the AAR from the recently acquired value of six and the GPC from zero. The tenth CLK pulse returns the base ten GPC to zero and elicits the GPC=O signal which is coupled to the CLOCK to turn it off. The ten CLK pulses 7 advance the AAR from its sixth position through its eleventh and zero positions and then to its fourth position. Accordingly, the one advancing pulse at the end of the second operational sequence and the ten advancing pulses during the third sequence step the twelve position AAR eleven times and effect a precessing or counting back of the AAR to the next lower position, and enables the addressing of the associated stage in the RA11.

The GPC= signal is also coupled to the reset inputs of the SQl, SQ2, and C devices to reset them. The resulting SQl and SQ2 signals are gated together and coupled to the D ACC27 to reset it to zero. The TQl-SQZ signal is also gated with the AAR=1 and AAR=I signals to produce a STOP or RESTART reconversion signal depending upon the status of the AAR. As the AAR is presently in its fourth position, AAR-:I is logically true and the RESTART reconversion signal is produced.

In the above manner the pence value stored in a stage of the RA11 has been reconverted into 9. pounds equivalent and the next cycle of three sequential operations started. In particular, the value of one stored in the fifth stage of the M is reconverted to a zero in that same stage and a remainder of ten which is stored in the CUC for use during the forthcoming first operational sequence upon the newly, addressed value in the fourth stage of the RA. Also, each of the bistable devices as well as the GPC, the CDC, and the D ACC are in the START reconversion condition set forth at the top of FIG. 2.

The operation upon the pence value of nine stored in the fourth stage or position of the RA11 is most similar to that of the value of one previously processed from the fifth RA position. The first of the next ten CLK pulses clears the fourth RA stage and sets the device C. The following nine CLK pulses are steered into the CUC which stored a remainder of ten, to thereby cause the CUC to store the value of nineteen which is transferred to the CDC. The device Y is set since the CUC contained a value other than zero; however, neither the devices W or X are set, as the CUC count did not reach its radix of twenty-four. The counting down of the CDC from nineteen to zero requires a train of one-hundred and ninety CLK pulses and produces seven base twenty-four CUC carries into the fourth stage of the RA and leaves a remainder of twenty-two in the CUC as shown in the RA/POS4 column of FIG. 7.

The AAR is again precessed, this time to its third position, to address the third column or stage in the RA which contains the pence value of nine, and the three operational sequences of the reconversion apparatus are again restarted.

Thereupon the remainder of twenty-two and the pence value of nine are added together in the CUC to form thirty-one, which exceeds its radix. Consequently the device W is set, representing twenty-four, and the CUC temporarily stores the value of seven. The value of seven is transferred to the CDC and the device X is set representing an additional CDC value of twenty-four. The X device being set prevents the device Y from being reset the first time the CDC reaches zero. Thus, the CDC is counted down from seven to zero and then from twentythree down to zero by a train of three-hundred and ten CLK pulses during the second sequence in RA position three. That amount of pulses is also applied to the CUC, generates twelve carries into the third stage of the RA, and leaves a remainder of twenty-two in the CUC. As depicted in FIG. 7, the twelve carry pulses into the third RA stage exceeds its radix of ten and propagates a carry out pulse into the fourth stage which is added to the previously entered value of seven to create an eight in that tens-of-pounds position.

Once again the AAR is precessed, now to AAR=2, for the addressing of column two of the RA which contains a four in the tens of pence position. As in the previous column position, the remainder in the CUC plus the added value from the RA stage exceeds the capacity of the CUC, causes the setting of first the W device and, upon transfer to the CDC, the setting of the X device. Accordingly, a train of two-hundred and sixty CLK pulses are required to count down the CDC and reset the device Y.

However, and with reference to FIG. 4, with the AAR:2-Y gated signal being true during the generation of these CLK pulses, only each tenth pulse is applied to the CUC. Thus both the CUC and the CDC are counted at the same rate. This departure from the normal sequence two operation is to enable the subject reconversion apparatus to operate more simply in that it reconverts pence to sterling values without also specifically identifying shillings and reconverting them to pounds. To accomplish this, the pence values in RA position one and two and the remainder from position three are stripped of their pound equivalents by counting the CUC and CDC at the same rate and steering the CUC carries into the third RA position, rather than the AAR positional address of two. As apparent from FIGS. 6 and 7, the second stage of the RA, which is the tens of shillings position, is not directly addressable and is accessable only through a carry condifrom the first RA position.

Returning to the example problem, the effective CUC value of twenty-six is divided by its radix twenty-four to create a yield in the form of a quotient of one, which is applied directly to the third RA stage, and a remainder of two. Since the third RA stage already contained a two, it is advanced to three, representing that pound value. The AAR is once again precessed, this time to produce the AAR=1 signal and the RESTART signal which is elicited for the last time.

The first operational sequence is performed upon the one pence value in the first RA position in the normal manner with one major exception, as illustrated in FIG. 2. The setting of the device C and AAR=l steers all subsequent CLK pulses into the D ACC27 and not into the CUC23. Thus, the one pence value stored in the least significant RA stage is cleared into the D ACC and not added to the remainder value of two held in the CUC. Accordingly, in this example, the transfer from the CUC to the CDC involves only the digital value of two, the previous remainder.

The second operational sequence is also modified by the AAR=1 condition. The CLK pulses required to count down the CDC are now coupled to the base twelve D ACC and not the base twenty-four CUC. Since the CDC holds the value of two, twenty CLK pulses are generated and added to the one pence values already stored in the D ACC. The insertion of a total of twentyone pulses into the D ACC yields a quotient carry into the then addressed first stage of the RA and a remainder of nine in the D ACC. The carry into the RA stage represents the resultant number of shillings. Had a large remainder been stored in the CUC, then more than nine carries could have been generated from the D ACC into the first RA stage and thus cause a tens carry to propagate into the second RA stage which represents the tens of shillings value.

The example problem has demonstrated the operation of the subject radix reconversion apparatus by reconverting the value of 19,941 pence, stored in the five least significant stages of the resultant accumulator, into 83-1-9, which is stored in the same accumulator stages as well as the pence accumulator.

The example problem and the descriptive material preceding it has presented an efficient and logically simple radix reconversion apparatus for accomplishing all of the objects and advantages of this invention. While the fundamental novel features of the subject apparatus has been shown and described with reference to a particular style of computer and its logic blocks, it will be apparent to those skilled in the art that variations may be made without departing from the spirit of the invention. By

changing the radices of the counting and storing elements and the rates of counting the butter memories, the primary accumulator can store values for reconversion to a mixed radix different than the decimal to sterling reconversion hereinabove described.

Iclairn:

1. Radix reconversion apparatus comprising:

a first accumulator having a plurality of sequentially addressable stages each storing a digital value in a first radix,

a pair of bufiier memories each opera-ting in a second radix and intercoupled for the transfer of the contents of one of the memories to the other,

said first buffer memory having an input and a radix carry output both coupled to the first accumulator,

said second butter memory having an input and a zero count carry output,

a second accumulator operating in a third radix and having an input and a radix carry output both coupled to a single stage of the first accumulator,

pulse generating, counting, and steering means coupled to the inputs of the buffer memories and the second accumulator and also coupled to the output of the first buffer memory and the second accumulator and advancing them all to an output status and coupling the outputs of the first bufier memory and the second accumulator to the first accumulator, and

said means having a generating control input coupled to the output of the second butter memory and terminating reconversion upon receipt of a zero count carry output.

2. The radix reconversion apparatus defined in claim 1 wherein:

the first radix is ten, the second radix is twenty-four and the third radix is twelve;

the pulse generating, counting, and steering means controls the advancing of the second accumulator, the first buffer memory, and the second butter memory to respective advancing rates of ten, ten, and one; also isolates the time of advancing the first butter memory from the advancing of the second accumulator; and also isolates the time that the output of the first buffer memory is coupled to the first accumulator from the time that the second accumulator is so coupled;

the reconversion apparatus provides mathematic division of the first radix values yielding quotients, in the form of the first memory carrying signals, and remainders; and further comprising radix extending a logic coupled between the buffer memories and the pulse generating, counting, and steering means and temporarily inhibiting said means from terminating reconversion whenever the radix of the first memory is exceeded prior to the transfer of its contents.

3. The radix reconversion apparatus defined in claim 2 wherein:

the pulse generating, counting, and steering means has an output producing a control signal responsive to a. radix of ten, and

the first memory has a count storing and adding means for retaining a remainder and adding it to the first radix value of a next addressed stage of the first accumulator.

4. The radix reconversion apparatus defined in claim 3 further comprising:

operational logic having a plurality of inputs which are controlled separately by the output of the pulse generating, counting, and steering means and the second memory upon attainment of the zero count status,

said operational logic having a plurality of outputs coupled to said means controlling the generation of pulses and terminating the operation of the entire reconversion apparatus.

5. Radix reconversion apparatus comprising:

a multistage resultant accumulator, each stage of which having a radix of ten, a tens carry output, and being discretely addressable in an order of significance;

a multiposition resultant accumulator address register coupled to the resultant accumulator for discretely addressing each stage;

a generator of clock pulses having an output coupled through the address register to the resultant accumulator;

a group pulse counter coupled between an input and the output of the generator and having an output producing radix ten control signals;

a first and a second radix twenty-four buffer memory coupled to the output of the group pulse counter and intercoupled for the transfer of the contents of the first memory to the second memor upon receipt of a first control signal from the group pulse counter;

said first bulfer memory having an input coupled to the output of the generator separately controlled by the tens carry output of the resultant accumulator and the first control signal from the group pulse counter and also having a radix carry output coupled to the resultant accumulator;

said second butler memory having an input coupled to the output of the group pulse counter and an output activated upon receipt of control signals equal to the contents transferred from the first memory, said second memory output being coupled to and controlling the generator; and

a radix twelve accumulator having an input coupled to the generator seperately controlled by the tens carry output of the least significant resultant accumulator stage and the first control signal from the group pulse counter during the addressing of the least significant stage and also having a radix carry output coupled to the least significant resultant accumulator stage.

6. The radix reconversion apparatus defined in claim 5 further comprising:

radix extending logic having a first and second set of inputs and an output,

said first set of inputs coupled to and controlled by the first memory output and the transfer of the contents from the first memory to the second memory,

said second set of inputs coupled to the group pulse counter and the second memory and separately controlled by the first control signal from the group pulse counter and the coincidence of a second memory output and a control signal from the group pulse counter, and

said output coupled in controlling relationship to the generator in response to control from the first set of inputs.

7. The radix reconversion apparatus defined in claim 5 further comprising:

a pair of reconversion operational control binary switching devices,

said switching devices having a plurality of inputs coupled and responsive to the output of the group pulse counter and the second bufier memory, and

said switching devices having a plurality of outputs coupled to the generator and the address register and producing a plurality of logically different output signals each regulating the generator, the last output signal also controlling the termination of the operation of the reconversion apparatus.

8. Radix reconversion apparatus comprising:

a resultant accumulator having a plurality of discretely addressed, base ten stages each having an input and a tens carry output and arranged in decimally significant order,

an accumulator address register having a plurality of sequential positions equal in number to the stages in the resultant accumulator and coupled to the inputs thereof for their discrete addressing,

a generator of clock pulses having on and off inputs and a pulse delivering output, the latter coupled through the address register to the stages of the resultant accumulator,

a base ten group pulse counter having an input connected to the output of the generator and a radix ten control signal output connected to the off input of the generator and also coupled to the on input of the generator,

a first and a second incrementally countable, base twenty-four buifer memory,

transfer means coupling the bufier memories together and responsive to a first control signal from the group pulse counter to transfer the contents of the first memory to the second memory,

said first memory having an input coupled to and controlled by the tens carry outputs of the resultant accumulator stages and coupled to the output of the generator for receiving pulses therefrom,

the input of the first memory also coupled to and controlled by the accumulator address register and further controlled by the first control signal from the group pulse counter to receive outputs from the generator subsequent thereto except during the addressing of the least significant resultant accumulator stage,

said first memory having a radix carry output coupled to the input of the addressed resultant accumulator stage,

said second memory being precessable, having an input coupled to the output of the group pulse counter, and having a zero count status output coupled to the off input of the generator, the control signals from the group pulse counter precessing the second memory and enabling its output, and

a base twelve pence accumulator having an input coupled to and controlled by the tens carry output of the least significant stage of the resultant accumulator and also coupled to the output of the generator for receiving pulses therefrom,

the input of the pence accumulator also coupled to and controlled by the accumulator address register and further controlled by the first control signal from the group pulse counter to receive outputs from the generator subsequent thereto during the addressing of the least significant resultant accumulator stage,

the output of the first buffer memory being coupled to one of the inputs of the first bistable element and controlling its setting to an exceed first memory radix state by a radix carry output signal from that memory,

the output of the group pulse counter being coupled to the other input of the first bistable element and controlling its resetting,

first coincident gating means having inputs coupled to the output of the first bistable device and the memory transfer means and having a setting control output connected to one of the inputs of the second bistable element,

the output of the second bistable element being coupled to the generator and inhibiting the output of the second buffer memory from turning off the generator during the time that the second bistable device is set, and

second coincident gating means having inputs coupled to the output of the second buffer memory and the output of the group pulse counter and having a resetting control output connected to the other input of the second bistable element.

10. The rad x reconversion apparatus defined in claim 8 further comprising:

a first and a. second binary switch each having a pair of inputs and a pair of logically inverted outputs,

all of said binary switch outputs being coupled to the on input of the generator and turning it on upon changes of binary status of the switches,

one input of the first switch coupled and responsive to the first output signal from the group pulse counter,

one input of the second switch coupled to the output of References Cited UNITED STATES PATENTS said pence accumulator having a radix carry output 3153228 10/1964 235 155 X coupled to the input of the least significant stage of 50 3,257,547 6/1966 Bernstem 235-455 the resultant accumulaton 3,350,708 10/1967 Adler 23s 15s X 9. The radix reconversion apparatus defined in claim 8 further comprising:

a first and a second settable and resettable bistable element each having a pair of inputs and an output, 55

MAYNARD R. WILBUR, Primary Examiner.

C. MILLER. Assistant Examiner. 

1. RADIX RECONVERSION APPARATUS COMPRISING: A FIRST ACCUMULATOR HAVING A PLURALITY OF SEQUENTIALLY ADDRESSABLE STAGES EACH STORING A DIGITAL VALUE IN A FIRST RADIX, A PAIR OF BUFFER MEMORIES EACH OPERATING IN A SECOND RADIX AND INTERCOUPLED FOR THE TRANSFER OF THE CONTENTS OF ONE OF THE MEMORIES TO THE OTHER, SAID FIRST BUFFER MEMORY HAVING AN INPUT AND A RADIX CARRY OUTPUT BOTH COUPLED TO THE FIRST ACCUMULATOR, SAID SECOND BUFFER MEMORY HAVING AN INPUT AND A ZERO COUNT CARRY OUTPUT, A SECOND ACCUMULATOR OPERATING IN A THIRD RADIX AND HAVING AN INPUT AND A RADIX CARRY OUTPUT BOTH COUPLED TO A SINGLE STAGE OF THE FIRST ACCUMULATOR, PULSE GENERATING, COUNTING, AND STEERING MEANS COUPLED TO THE INPUTS OF THE BUFFER MEMORIES AND THE SECOND ACCUMULATOR AND ALSO COUPLED TO THE OUTPUT OF THE FIRST BUFFER MEMORY AND THE SECOND ACCUMULATOR AND ADVANCING THEM ALL TO AN OUTPUT STATUS AND COUPLING THE OUTPUTS OF THE FIRST BUFFER MEMORY AND THE SECOND ACCUMULATOR TO THE FIRST ACCUMULATOR, AND SAID MEANS HAVING A GENERATING CONTROL INPUT COUPLED TO THE OUTPUT OF THE SECOND BUFFER MEMORY AND TERMINATING RECONVERSION UPON RECEIPT OF A ZERO COUNT CARRY OUTPUT. 